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1 ? fn4659.11 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2001, 2002, 2004. all rights reserved. all other trademarks mentioned are the property of their respective owners. HC55120, hc55121, hc55 130, hc55131, hc55140, hc55141, hc55142, hc551 43, hc55150, hc55151 low power unislic14 family the unislic14 is a family of ultra low power slics. the feature set and common pinouts of the unislic14 family positions it as a universal solution for: plain old telephone service (pots), pbx, central office, loop carrier, fiber in the loop, isdn-ta and nt1+, pairgain and wireless local loop. the unislic14 family achieves its ultra low power operation through: its automatic single and dual battery selection (based on line length) and battery tracki ng anti clipping to ensure the maximum loop coverage on the lowest battery voltage. this architecture is ideal for power critical applications such as isdn nt1+, pairgain and wireless local loop products. the unislic14 family has many user programmable features. this family of slics delivers a low noise, low component count solution for central office and loop carrier universal voice grade designs. the product family integrates advanced pulse metering, test and signaling capabilities, and zero crossing ring control. the unislic14 family is design ed in the intersil ?latch? free bonded wafer process. this proces s dielectrically isolates the active circuitry to eliminate an y leakage paths as found in our competition?s ji process. this makes the unislic14 family compliant with ?hot plug? requirements and operation in harsh outdoor environments. features ? ultra low active power (oht) < 60mw ? single/dual battery operation ? automatic silent battery selection ? power management/shutdown ? battery tracking anti clipping ? single 5v supply with 3v compatible logic ? zero crossing ring control - zero voltage on/zero current off ? tip/ring disconnect ? pulse metering capability ? 4 wire loopback ? programmable current feed ? programmable resistive feed ? programmable loop detect threshold ? programmable on-hook and off-hook overheads ? programmable overhead for pulse metering ? programmable polarity reversal time ? selectable transmit gain 0db/-6db ? 2 wire impedance set by single network ? loop and ground key detectors ? on-hook transmission ? common pinout ? pb-free available ? hc55121 - polarity reversal ? hc55130 - -63db longitudinal balance ? hc55140 - polarity reversal - ground start - line voltage measurement - 2 wire loopback - -63db longitudinal balance ? hc55142 - polarity reversal - ground start - line voltage measurement -2.2v rms pulse metering - 2 wire loopback ? hc55150 - polarity reversal - line voltage measurement -2.2v rms pulse metering - 2 wire loopback related literature ? an9871, user?s guide for unislic14 eval board ? an9903, unislic14 and ti tcm38c17 rrly dt dr tip ring v bh v cc ring and test relay drivers ring trip detector v bl bgnd battery selection and bias network zero current 2-wire interface crossing trly1 trly2 v tx v rx c1 c2 c3 gkd _lvm roh rd cdc rdc_rac zt c h loop current detector ptg ilim state decoder and detector logic gkd /loop length detector rsync_rev shd 4-wire interface vf signal path line feed control c4 c5 crt_rev_lvm polarity reversal pulse metering spm signal path agnd block diagram data sheet july 2004
2 ordering information part number max loop current (ma) polarity reversal gnd start gnd key line voltage measurement ? pulse metering 2 test relay drivers 2 wire loop- back ? longitudinal balance temp range (c) pkg. dwg. # HC55120cb 30 ? 53db 0 to 70 m28.3 soic HC55120cbz pb-free (note) 30 ? 53db 0 to 70 m28.3 soic HC55120cm 30 ? 53db 0 to 70 n28.45 plcc hc55121ib 30 ?? ? ? 53db -40 to 85 m28.3 soic hc55121ibz pb-free (note) 30 ?? ? ? 53db -40 to 85 m28.3 soic hc55121im 30 ?? ? ? 53db -40 to 85 n28.45 plcc hc55130ib 45 63db -40 to 85 m28.3 soic hc55130ibz pb-free (note) 45 63db -40 to 85 m28.3 soic hc55130ibz96 pb-free (note) 45 63db -40 to 85 m28.3 soic hc55130im 45 63db -40 to 85 n28.45 plcc hc55131im 45 ? 63db -40 to 85 n32.45x55 plcc hc55140ib 45 ??? ? ? 63db -40 to 85 m28.3 soic hc55140ibz pb-free (note) 45 ??? ? ? 63db -40 to 85 m28.3 soic hc55140im 45 ??? ? ? 63db -40 to 85 n28.45 plcc hc55141im 45 ??? ? ? ? 63db -40 to 85 n32.45x55 plcc hc55142ib 45 ??? ? ? ? 63db -40 to 85 m28.3 soic hc55142ibz pb-free (note) 45 ??? ? ? ? 63db -40 to 85 m28.3 soic hc55142im 45 ??? ? ? ? 63db -40 to 85 n28.45 plcc hc55143im 45 ??? ? ? ? ? 63db -40 to 85 n32.45x55 plcc hc55150cb 45 ???? 55db 0 to 70 m28.3 soic hc55150cbz pb-free (note) 45 ???? 55db 0 to 70 m28.3 soic hc55150cm 45 ???? 55db 0 to 70 n28.45 plcc hc55151cm 45 ????? 55db 0 to 70 n32.45x55 plcc hc5514xeval1 evaluation board ? available by placing slic in test mode. note: intersil pb-free products employ special pb-free material sets ; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and pb-f ree soldering operations. inters il pb-free products are msl clas sified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020b. HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
3 device operating modes c3 c2 c1 description HC55120 hc55121 hc55130/1 hc55140/1 hc55142/3 hc55150/1 0 0 0 open circuit 4-wire loopback ?????? 0 0 1 ringing ?????? 0 1 0 forward active ?????? 0 1 1 test forward active 2 wire loopback and line voltage measurement ???? 1 0 0 tip open ground start ?? 101reserved ?????? 1 1 0 reverse active ???? 1 1 1 test reverse active line voltage measurement ??? HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
4 absolute m aximum ratings t a = 25c thermal information temperature, humidity storage temperature range . . . . . . . . . . . . . . . . .-65c to 150c operating temperature range . . . . . . . . . . . . . . .-40c to 110c operating junction temperature range . . . . . . . .-40c to 150c power supply (-40c t a 85c) supply voltage v cc to gnd . . . . . . . . . . . . . . . . . . . . -0.4v to 7v supply voltage v bl to gnd . . . . . . . . . . . . . . . . . . . .-v bh to 0.4v supply voltage v bh to gnd, continuous . . . . . . . . . -75v to 0.4v supply voltage v bh to gnd, 10ms . . . . . . . . . . . . . . -80v to 0.4v relay driver ring relay supply voltage . . . . . . . . . . . . . . . . . . . . . . 0v to 14v ring relay current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50ma digital inputs, outputs (c1, c2, c3, c4, c5, shd , gkd _lvm ) input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to v cc output voltage (shd , gkd _lvm not active) . . . . . -0.4v to v cc output current (shd , gkd _lvm) . . . . . . . . . . . . . . . . . . . . . 5ma esd rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500v gate count. . . . . . . . . . . . . . . . . . . . . . . 543 transistors, 51 diodes tipx and ringx te rminals (-40c t a 85c) tipx or ringx current . . . . . . . . . . . . . . . . . . . . -100ma to 100ma thermal resistance (typical, note 1) ja 28 lead plcc package. . . . . . . . . . . . . . . . . . . . . . 52c/w 28 lead soic package . . . . . . . . . . . . . . . . . . . . . . 45c/w 32 lead plcc package. . . . . . . . . . . . . . . . . . . . . . 66.2c/w continuous power dissipation at 85c 28 lead plcc package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5w 28 lead soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.0w 32 lead plcc package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.4w lead temperature (soldering 10s). . . . . . . . . . . . . . . . . . . . . . . . 300c (plcc, soic - lead tips only) derate above 70c tip and ring terminals tipx or ringx, current, pulse < 10ms, t rep > 10s . . . . . . . . . .2a tipx or ringx, current, pulse < 1ms, t rep > 10s . . . . . . . . . . .5a tipx or ringx, current, pulse < 10 s, t rep > 10s . . . . . . . . .15a tipx or ringx, current, pulse < 1 s, t rep > 10s . . . . . . . . . .20a tipx or ringx, pulse < 250ns, t rep > 10s 20a caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mount ed on an evaluation pc board in free air. typical operating conditions these represent the conditions u nder which the device was developed and are suggested as guidelines. parameter conditions min typ max units ambient temperature HC55120, hc55150/1 0 - 70 c hc55121, hc55130/1, hc55140/1, hc55142/3 -40 - 85 c v bh with respect to gnd -58 - -8 v v bl with respect to gnd v bh -0 v v cc with respect to gnd 4.75 - 5.25 v HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
5 electrical specifications t a = -40c to 85c, v cc = +5v 5%, v bh = -48v, v bl = -24v, ptg = open, r p1 = r p2 = 0 ?, z t = 120k ? , r lim = 38.3k ? , r d = 50k ? , rdc_rac = 20k ? , r oh = 40k ? , c h = 0.1 f, c dc = 4.7 f, c rt/rev = 0.47 f, gnd = 0v, rl = 600 ? . unless otherwise specified. (?) symbol used to indicate the test applies to the part. (na) symbol used to indicate the test does not apply to the part. parameter test conditions min typ max units HC55120 hc55121 hc55130/1 hc55140/1 hc55142/3 hc55150/1 2-wire port overload level, off hook forward and reverse 1% thd, i dcmet 18ma (note 2, figure 1) 3.2 - - v peak forward only ? forward only ??? overload level, on hook forward and reverse 1% thd, idcmet 5ma (note 3, figure 1) 1.3 - - v peak forward only ? forward only ??? input impedance (into tip and ring) - z t /200 - ? ?????? longitudinal impedance (tip, ring) forward and reverse 0 < f < 100hz (note 4, figure 2) - 0 - ? /wire forward only ? forward only ??? longitudinal current limit (tip, ring) on-hook, off-hook (active), r l = 736 ? forward and reverse no false detections, (loop current), lb > 45db (notes 5, 6, figures 3a, 3b) 28 - - ma rms / wire forward only ? forward only ??? figure 1. overload level (off hook, on hook) fig ure 2. longitudinal impedance figure 3a. longitudinal current limit on-hook (active) figure 3b. longitudinal current limit off-hook (active) tip v tx ring vrx e rx r l v tr i dcmet e l v t c 0 < f < 100hz v r lz t = v t /a t lz r = v r /a r 1v rms 300 ? 300 ? tip ring a t a r v tx vrx e l 368 ? 368 ? a tip ring shd c 10 f c 10 f a v tx vrx e l 368 ? 368 ? c a tip ring shd a v tx vrx v tx HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
6 off-hook longitudinal balance min min min min min min longitudinal to metallic (note 7) forward and reverse ieee 455 - 1985, r lr , r lt = 368 ? normal polarity: forward only forward only 0.2khz < f < 1.0khz, 0c to 70c - - - db 53 na na na na 55 1.0khz < f < 3.4khz, 0c to 70c - - - db 53 na na na na 55 0.2khz < f < 1.0khz, -40c to 85c - - - db na 53 63 63 63 na 1.0khz < f < 3.4khz, -40c to 85c - - - db na 53 58 58 58 na reverse polarity 0.2khz < f < 3.4khz, (figure 4) - - - db na 53 na 58 58 55 min min min min min min longitudinal to metallic (note 7) forward and reverse r lr , r lt = 300 ? , normal polarity: forward only forward only 0.2khz < f < 1.0khz, 0c to 70c - - - db 53 na na na na 55 1.0khz < f < 3.4khz, 0c to 70c - - - db 53 na na na na 55 0.2khz < f < 1.0khz, -40c to 85c - - - db na 53 63 63 63 na 1.0khz < f < 3.4khz, -40c to 85c - - - db na 53 58 58 58 na reverse polarity 0.2khz < f < 3.4khz, (figure 4) - - - db na 53 na 58 58 55 min min min min min min longitudinal to 4-wire (note 9) (forward and reverse) normal polarity: forward only forward only 0.2khz < f < 1.0khz, 0c to 70c - - - db 53 na na na na 61 1.0khz < f < 3.4khz, 0c to 70c - - - db 53 na na na na 61 0.2khz < f < 1.0khz, -40c to 85c - - - db na 53 63 63 63 na 1.0khz < f < 3.4khz, -40c to 85c - - - db na 53 58 58 58 na reverse polarity 0.2khz < f < 3.4khz, (figure 4) - - db na 53 na 58 58 61 metallic to longitudinal (note 10) forward and reverse fcc part 68, para 68.310 (note 8) 0.2khz < f < 3.4khz, (figure 5) 40 50 - db forward only ? forward only ??? 4-wire to longitudinal (note 11) forward and reverse 0.2khz < f < 3.4khz, (figure 5) 40 - - db forward only ? forward only ??? electrical specifications t a = -40c to 85c, v cc = +5v 5%, v bh = -48v, v bl = -24v, ptg = open, r p1 = r p2 = 0 ?, z t = 120k ? , r lim = 38.3k ? , r d = 50k ? , rdc_rac = 20k ? , r oh = 40k ? , c h = 0.1 f, c dc = 4.7 f, c rt/rev = 0.47 f, gnd = 0v, rl = 600 ? . unless otherwise specified. (?) symbol used to indicate the test applies to the part. (na) symbol used to indicate the test does not apply to the part. (continued) parameter test conditions min typ max units HC55120 hc55121 hc55130/1 hc55140/1 hc55142/3 hc55150/1 HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
7 figure 4. longitudinal to metallic and longitudinal to 4-wire balance figure 5. metallic to longitudinal and 4-wire to longitudinal balance 2-wire return loss forward and reverse 0.2khz to 1.0khz (note 12, figure 6) 30 35 - db forward only ? forward only ??? 1.0khz to 3khz (note 12, figure 6) 23 25 - db 3khz to 3.4khz (note 12, figure 6) 21 23 - db tip idle voltage (user programmable) tipx idle voltage active, i l < 5ma -2.6 -2.2 -1.8 v forward only ? forward only ??? forward and reverse ring idle voltage (user programmable) ringx idle voltage forward and reverse active, i l < 5ma -46.4 -45.3 -44.2 v forward only ? forward only ??? tip open, i l < 5ma -46.4 -45.3 -44.2 v v tr forward and reverse active, i l < 5ma 41 43.1 45 v forward only ? forward only ??? v tr(roh) pulse metering forward and reverse active, i l 8.5ma, r oh = 50k ? 36 38.1 - v na ? na na ?? figure 6. two-wire return loss figure 7. overload level (4-wir e transmit port), output offset voltage and harmonic distortion electrical specifications t a = -40c to 85c, v cc = +5v 5%, v bh = -48v, v bl = -24v, ptg = open, r p1 = r p2 = 0 ?, z t = 120k ? , r lim = 38.3k ? , r d = 50k ? , rdc_rac = 20k ? , r oh = 40k ? , c h = 0.1 f, c dc = 4.7 f, c rt/rev = 0.47 f, gnd = 0v, rl = 600 ? . unless otherwise specified. (?) symbol used to indicate the test applies to the part. (na) symbol used to indicate the test does not apply to the part. (continued) parameter test conditions min typ max units HC55120 hc55121 hc55130/1 hc55140/1 hc55142/3 hc55150/1 e l v tr c r lt r lr 2.16 f tip ring v tx vrx v tx e tr v l c r lt r lr 300 ? 300 ? 2.16 f tip ring v tx vrx e rx v s z d r lr r r z in v m tip ring v tx vrx e g r l z l v tr tip ring v tx vrx v tx 600 ? HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
8 4-wire transmit port (v tx ) overload level, off hook (i l 18ma) forward and reverse (z l > 20k ? , il 1% thd) (note 13, figure 7) t a = 0c to 85c t a = -40c to 0c 3.2 - - v peak forward only ? forward only ??? 3.0 - - v peak overload level, on hook (i l 5ma) forward and reverse (z l > 20k ? , 1% thd) (note 14, figure 7) 1.3 - - v peak forward only ? forward only ??? v tx output offset voltage forward and reverse e g = 0, z l = , (note 15, figure 7) -200 - 200 mv forward only ? forward only ??? output impedance (guaranteed by design) 0.2khz < f < 03.4khz - 0.1 1 ? ?????? 4-wire receive port (vrx) vrx input impedance (guaranteed by design) 0.2khz < f < 3.4khz - 500 600 k ? ?????? frequency response (off-hook) 2-wire to 4-wire forward and reverse relative to 0dbm at 1.0khz, e rx = 0v forward only ? forward only ??? 0.3khz < f < 3.4khz -0.15 - 0.15 db f = 8.0khz (note 16, figure 8) - 0.24 0.5 db f = 12khz (note 16, figure 8) - 0.58 1.0 db f = 16khz (note 16, figure 8) - 1.0 1.5 db 4-wire to 2-wire forward and reverse relative to 0dbm at 1.0khz, e g = 0v 0.3khz < f < 3.4khz -0.15 - 0.15 db forward only ? forward only ??? f = 8khz (note 17, figure 8) -0.5 0.24 - db f = 12khz (note 17, figure 8) -1.0 0.58 - db f = 16khz (note 17, figure 8) -1.5 1.0 - db 4-wire to 4-wire forward and reverse relative to 0dbm at 1.0khz, e g = 0v forward only ? forward only ??? 0.3khz < f < 3.4khz (note 18, figure 8) -0.15 - 0.15 db 8khz, 12khz, 16khz (note 18, figure 8) -0.5 0 0.5 db figure 8. frequency response, insertion loss, gain tracking and harmonic distortion figure 9. idle channel noise electrical specifications t a = -40c to 85c, v cc = +5v 5%, v bh = -48v, v bl = -24v, ptg = open, r p1 = r p2 = 0 ?, z t = 120k ? , r lim = 38.3k ? , r d = 50k ? , rdc_rac = 20k ? , r oh = 40k ? , c h = 0.1 f, c dc = 4.7 f, c rt/rev = 0.47 f, gnd = 0v, rl = 600 ? . unless otherwise specified. (?) symbol used to indicate the test applies to the part. (na) symbol used to indicate the test does not apply to the part. (continued) parameter test conditions min typ max units HC55120 hc55121 hc55130/1 hc55140/1 hc55142/3 hc55150/1 e g r l 600 ? v tr e rx tip ring vrx v tx v tx ptg open 600 ? v tr r l tip ring vrx v tx v tx HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
9 insertion loss 2-wire to 4-wire forward and reverse 0dbm, 1khz ? ??? ptg = open (note 19, figure 8) -0.2 - 0.2 db forward only forward only ptg = gnd (note 20, figure 8) -6.22 -6.02 -5.82 db 4-wire to 2-wire forward and reverse 0dbm, 1khz (note 21, figure 8) -0.2 - 0.2 db forward only ? forward only ??? gain tracking (ref = -10dbm, at 1.0khz) 2-wire to 4-wire forward and reverse -40dbm to +3dbm (note 22, figure 8) -0.1 - 0.1 db forward only ? forward only ??? -55dbm to -40dbm (note 22, figure 8) -0.2 - 0.2 db 4-wire to 2-wire forward and reverse -40dbm to +3dbm (note 23, figure 8) -0.1 - 0.1 db forward only ? forward only ??? -55dbm to -40dbm (note 23, figure 8) -0.2 - 0.2 db noise idle channel noise at 2-wire c-message weighting - 10.5 13 dbrnc forward only ? forward only ??? forward and reverse psophometric weighting (note 24, note 30, figure 9) - -79.5 -77 dbmp idle channel noise at 4-wire c-message weighting - 10.5 13 dbrnc forward only ? forward only ??? forward and reverse psophometrical weighting (note 25, note 30, figure 9) - -79.5 -77 dbmp harmonic distortion 2-wire to 4-wire forward and reverse 0dbm, 0.3khz to 3.4khz (note 26, figure 7) - -67 -50 db forward only ? forward only ??? 4-wire to 2-wire forward and reverse 0dbm, 0.3khz to 3.4khz (note 27, figure 8) - -67 -50 db forward only ? forward only ??? figure 10. constant lo op current tolerance figure 11. tipx voltage electrical specifications t a = -40c to 85c, v cc = +5v 5%, v bh = -48v, v bl = -24v, ptg = open, r p1 = r p2 = 0 ?, z t = 120k ? , r lim = 38.3k ? , r d = 50k ? , rdc_rac = 20k ? , r oh = 40k ? , c h = 0.1 f, c dc = 4.7 f, c rt/rev = 0.47 f, gnd = 0v, rl = 600 ? . unless otherwise specified. (?) symbol used to indicate the test applies to the part. (na) symbol used to indicate the test does not apply to the part. (continued) parameter test conditions min typ max units HC55120 hc55121 hc55130/1 hc55140/1 hc55142/3 hc55150/1 600 ? v tr r l tip ring v tx vrx r lim r lim 38.3k ? tip ring s r 1 7k ? v bh v tx vrx i r1 HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
10 battery feed characteristics constant loop current tolerance 18ma il 45ma, forward only ? forward only ??? i l = 26.5ma, r lim = 38.3k ? forward and reverse (note 27, figure 10) 0.92i l i l 1.08i l ma tip open state tipx leakage current s = closed (figure 11) - - -200 a ?????? tip open state ringx current r 1 = 0 ? , v bh = -48v, r lim = 38.3k ? 22.6 26.8 31 ma ?????? r 1 = 2.5k ? , v bh = -48v (figure 11) 15.5 17.1 18.2 ma tip open state ringx voltage 5ma < i r1 < 26ma (figure 11) - 42.8 - v ?????? tip voltage (ground start) active state, (s open) r 1 = 150 ? (figure 11) -5.3 -4.8 -4.3 v na na na ?? na tip voltage (ground start) active state, (s closed) tip lead to ?? -48v through 7k ? , ring lead to ground through 150 ? (figure 11) -5.3 -4.8 -4.3 v na na na na open circuit state loop current (active) r l = 0 ? -20 0 20 a ?????? loop current detector programmable threshold i lth = (500/ r d ) 5ma, 0.9i lth i lth 1.1i lth ma forward only ? forward only ??? forward and reverse i lth = 8.5ma r d = 58.8k ? ground key detector ground key detector threshold tip/ring current difference tip open 5 8 11 ma ?? na ?? na active (note 29, r1 = 2.5k ? , figure 12) 12.5 20 27.5 ma line voltage measurement pulse width (gkd _lvm ) pulse width = (20)(c rev... /i lim ) 0.32 0.36 0.4 ms/v na na na ??? ring trip detector (dt, dr) ring trip comparator current source res = 2m ? -2- a ?????? input common-mode range source res = 2m ? -- 200 v ?????? electrical specifications t a = -40c to 85c, v cc = +5v 5%, v bh = -48v, v bl = -24v, ptg = open, r p1 = r p2 = 0 ?, z t = 120k ? , r lim = 38.3k ? , r d = 50k ? , rdc_rac = 20k ? , r oh = 40k ? , c h = 0.1 f, c dc = 4.7 f, c rt/rev = 0.47 f, gnd = 0v, rl = 600 ? . unless otherwise specified. (?) symbol used to indicate the test applies to the part. (na) symbol used to indicate the test does not apply to the part. (continued) parameter test conditions min typ max units HC55120 hc55121 hc55130/1 hc55140/1 hc55142/3 hc55150/1 HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
11 ring relay driver v sat at 30ma i ol = 30ma - 0.2 0.5 v ?????? v sat at 40ma i ol = 40ma - 0.52 0.8 v ?????? off state leakage current v oh = 13.2v - 0.1 10 a ?????? test relay driver (trly1, trly2) v sat at 30ma i ol = 30ma - 0.3 0.5 v na na na/ ? na/ ? na/ ? na/ ? v sat at 40ma i ol = 40ma - 0.65 1.3 v na na na/ ? na/ ? na/ ? na/ ? off state leakage current v oh = 13.2v - - 10 ananana/ ? na/ ? na/ ? na/ ? figure 12. ground key detect digital inputs (c1, c2, c3, c4, c5) input low voltage, v il 0-0.8 v ?????? input high voltage, v ih 2.0 - v cc v ?????? input low current, i il v il = 0.4v - - -10 a ?????? input high current, i ih v ih = 2.5v - 25 50 a ?????? detector outputs (shd , gkd _lvm ) shd output low voltage, v ol forward, reverse i ol = 1ma - - 0.5 v forward only ? forward only ??? shd output high voltage, v oh forward, reverse i oh = 100 a2.7--vforward only ? forward only ??? gkd _lvm output low voltage, v ol forward and tip open i ol = 1ma r 1 = 2.5k ? (figure 11) --0.5 v gkd gkd na gkd _ lvm gkd _ lvm lvm gkd _lvm output high voltage, v oh forward and tip open i oh = 100 a2.7--vgkd gkd na gkd _ lvm gkd _ lvm lvm internal pull-up resistor - 15 - k ? ?????? electrical specifications t a = -40c to 85c, v cc = +5v 5%, v bh = -48v, v bl = -24v, ptg = open, r p1 = r p2 = 0 ?, z t = 120k ? , r lim = 38.3k ? , r d = 50k ? , rdc_rac = 20k ? , r oh = 40k ? , c h = 0.1 f, c dc = 4.7 f, c rt/rev = 0.47 f, gnd = 0v, rl = 600 ? . unless otherwise specified. (?) symbol used to indicate the test applies to the part. (na) symbol used to indicate the test does not apply to the part. (continued) parameter test conditions min typ max units HC55120 hc55121 hc55130/1 hc55140/1 hc55142/3 hc55150/1 tip ring shd 2.5k ? v tx vrx HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
12 power dissipation (v bh = -48v, v bl = -24v) open circuit state c1, c2, c3 = 0, 0, 0 - 25 - mw forward only ? forward only ??? on-hook, active c1, c2, c3 = 0, 1, 0 c1, c2, c3 = 1, 1, 0 ? ??? forward and reverse i l = 0ma, longitudinal current = 0ma -52- mwforward only ? forward only ??? power supply currents (v bh = -48v, v bl = -24v) v cc current, i cc open circuit state - 2.25 3.0 ma forward only ? forward only ??? v bh current, i bh - 0.3 0.45 ma forward only ? forward only ??? v bl current, i bl - 0.022 0.035 ma forward only ? forward only ??? v cc current, i cc forward and reverse active state i l = 0ma, longitudinal current = 0ma - 2.7 3.6 ma forward only ? forward only ??? v bh current, i bh forward and reverse - 0.8 1.06 ma forward only ? forward only ??? v bl current, i bl forward and reverse - - 0.01 ma forward only ? forward only ??? power supply rejection ratios v cc to 2 or 4 wire port forward and reverse active state r l = 600 ? 50hz < f < 3400hz, v in =100mv - 40 - db forward only ? forward only ??? v bh to 2 or 4 wire port forward and reverse - 40 - db forward only ? forward only ??? v bl to 2 or 4 wire port forward and reverse - 40 - db forward only ? forward only ??? temperature guard junction threshold temperature - 175 - c ? ????? electrical specifications t a = -40c to 85c, v cc = +5v 5%, v bh = -48v, v bl = -24v, ptg = open, r p1 = r p2 = 0 ?, z t = 120k ? , r lim = 38.3k ? , r d = 50k ? , rdc_rac = 20k ? , r oh = 40k ? , c h = 0.1 f, c dc = 4.7 f, c rt/rev = 0.47 f, gnd = 0v, rl = 600 ? . unless otherwise specified. (?) symbol used to indicate the test applies to the part. (na) symbol used to indicate the test does not apply to the part. (continued) parameter test conditions min typ max units HC55120 hc55121 hc55130/1 hc55140/1 hc55142/3 hc55150/1 HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
13 notes 2. overload level (two-wire port, off hook) - the overload level is specified at the 2-wire port (v tr ) with the signal source at the 4-wire receive port (e rx ). r l = 600 ? , i dcmet 18ma. increase the amplitude of e rx until 1% thd is measured at v tr . reference figure 1. 3. overload level (two-wire port, on hook) - the overload level is specified at the 2-wire port (v tr ) with the signal source at the 4-wire receive port (e rx ). r l = , i dcmet = 0ma. increase the amplitude of e rx until 1% thd is measured at v tr . reference figure 1. 4. longitudinal impedance - the longitudinal impedance is computed using the following equations, where tip and ring voltages are referenced to ground. l zt , l zr , v t , v r , a r and a t are defined in figure 2. (tip) l zt = v t /a t (ring) l zr = v r /a r where: e l = 1v rms (0hz to 100hz) 5. longitudinal current limit (on-hook active) - on-hook longitudinal current limit is det ermined by increasing the (60hz) amplitude of e l (figure 3a) until the 2-wire longitudinal current is greater than 28ma rms /wire. under this condition, shd pin remains low (no false detection) and the 2-wire to 4-wire longitudinal balance is verified to be greater than 45db (lb 2-4 = 20log vtx/e l ). 6. longitudinal current limit (off-hook active) - off-hook longitudinal current limit is det ermined by increasing the (60hz) amplitude of e l (figure 3b) until the 2-wire longitudinal current is greater than 28ma rms /wire. under this condition, shd pin remains high (no false detection) and the 2-wire to 4-wire longitudinal balance is verified to be greater than 45db (lb 2-4 = 20log vtx/e l ). 7. longitudinal to metallic balance - the longitudinal to metallic balance is computed using the following equation: blme = 20 log (e l /v tr ), where: e l and v tr are defined in figure 4. 8. metallic to longitudinal fcc part 68, para 68.310 - the metallic to longitudinal balanc e is defined in this spec. 9. longitudinal to four-wire balance - the longitudinal to 4-wire balance is computed using the following equation: blfe = 20 log (e l /v tx ), e l and v tx are defined in figure 4. 10. metallic to longitudinal balance - the metallic to longitudinal balance is computed using the following equation: bmle = 20 log (e tr /v l ), e rx = 0 where: e tr, v l and e rx are defined in figure 5. 11. four-wire to longitudinal balance - the 4-wire to longitudinal balance is computed using the following equation: bfle = 20 log (e rx /v l ), e tr = source is removed. where: e rx, v l and e tr are defined in figure 5. 12. two-wire return loss - the 2-wire return loss is computed using the following equation: r = -20 log (2v m /v s ) where: z d = the desired impedance; e.g., the characteristic impedance of the line, nominally 600 ?. (reference figure 6). 13. overload level (4-wire port off-hook) - the overload level is specified at the 4-wire transmit port (v tx ) with the signal source (e g ) at the 2-wire port, z l = 20k ?, r l = 600 ? (reference figure 7). increase the amplitude of e g until 1% thd is measured at v tx . note the ptg pin is open, and the gain from the 2-wire port to the 4-wire port is equal to 1. 14. overload level (4-wire port on-hook) - the overload level is specified at the 4-wire transmit port (v tx ) with the signal source (e g ) at the 2-wire port, z l = 20k ?, r l = (reference figure 7). increase the amplitude of e g until 1% thd is measured at v tx . note the ptg pin is open, and the gain from the 2-wire port to the 4-wire port is equal to 1. 15. output offset voltage - the output offset voltage is specified with the following conditions: e g = 0, r l = 600 ? , z l = and is measured at v tx . e g , r l , v tx and z l are defined in figure 7. 16. two-wire to four-wire frequency response - the 2-wire to 4-wire frequency response is measured with respect to e g = 0dbm at 1.0khz, e rx = 0v (vrx input floating), r l = 600 ? . the frequency response is computed using the following equation: f 2-4 = 20 log (v tx /v tr ), vary frequency from 300hz to 3.4khz and compare to 1khz reading. v tx , v tr , r l and e g are defined in figure 8. 17. four-wire to two-wire frequency response - the 4-wire to 2- wire frequency response is measured with respect to e rx =0dbm at 1.0khz, e g source removed from circuit, r l = 600 ? . the frequency response is computed using the following equation: f 4-2 = 20 log (v tr /e rx ), vary frequency from 300hz to 3.4khz and compare to 1khz reading. v tr , r l and e rx are defined in figure 8. 18. four-wire to four-wire frequency response - the 4-wire to 4-wire frequency response is measured with respect to e rx = 0dbm at 1.0khz, e g source removed from circuit, r l =600 ? . the frequency response is computed using the following equation: f 4-4 = 20 log (v tx /e rx ), vary frequency from 300hz to 3.4khz and compare to 1khz reading. v tx , r l and e rx are defined in figure 8. 19. two-wire to four-wire insertion loss (ptg = open) - the 2-wire to 4-wire insertion loss is measured with respect to e g = 0dbm at 1.0khz input signal, e rx = 0 (vrx input floating), r l = 600 ? and is computed using the following equation: l 2-4 = 20 log (v tx /v tr ) where: v tx , v tr , r l and e g are defined in figure 8. (note: the fuse resistors, r f , impact the insertion loss. the specified insertion loss is for r f1 = r f2 = 0). 20. two-wire to four-wire insertion loss (ptg = agnd) - the 2-wire to 4-wire insertion loss is measured with respect to e g = 0dbm at 1.0khz input signal, e rx = 0 (vrx input floating), r l = 600 ? and is computed using the following equation: l 2-4 = 20 log (v tx /v tr ) where: v tx , v tr , r l and e g are defined in figure 8. (note: the fuse resistors, r f , impact the insertion loss. the specified insertion loss is for r f1 = r f2 = 0). 21. four-wire to two-wire insertion loss - the 4-wire to 2-wire insertion loss is measured based upon e rx = 0dbm, 1.0khz input signal, e g source removed from circuit, r l = 600 ? and is computed using the following equation: l 4-2 = 20 log (v tr /e rx ) where: v tr , r l and e rx are defined in figure 8. 22. two-wire to four-wire gain tracking - the 2-wire to 4-wire gain tracking is referenced to measurements taken for e g = -10dbm, 1.0khz signal, e rx = 0 (vrx output floating), r l = 600 ? and is computed using the following equation. g 2-4 = 20 ? log (v tx /v tr ) vary amplitude -40dbm to +3dbm, or -55dbm to -40dbm and compare to -10dbm reading. v tx , r l and v tr are defined in figure 8. HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
14 23. four-wire to two-wire gain tracking - the 4-wire to 2-wire gain tracking is referenced to measurements taken for e rx = -10dbm, 1.0khz signal, e g source removed from circuit, r l = 600 ? and is computed using the following equation: g 4-2 = 20 ? log (v tr /e rx ) vary amplitude -40dbm to +3dbm, or -55dbm to -40dbm and compare to -10dbm reading. v tr , r l and e rx are defined in figure 8. the level is specified at the 4-wire receive port and referenced to a 600 ? impedance level. 24. two-wire idle channel noise - the 2-wire idle channel noise at v tr is specified with the 2-wire port terminated in 600 ? (r l ) and with the 4-wire receive port (vtx) floating (reference figure 9). 25. four-wire idle channel noise - the 4-wire idle channel noise at v tx is specified with the 2-wire port terminated in 600 ? (r l ). the noise specification is with respect to a 600 ? impedance level at v tx . the 4-wire receive port (vtx) floating (reference figure 9). 26. harmonic distortion (2-wire to 4-wire) - the harmonic distortion is measured within the voice band with the following conditions. e g = 0dbm at 1khz, r l = 600 ? . measurement taken at v tx . (reference figure 7). 27. harmonic distortion (4-wire to 2-wire) - the harmonic distortion is measured within the voice band with the following conditions. e rx = 0dbm0. vary frequency between 300hz and 3.4khz, r l = 600 ? . measurement taken at v tr . (reference figure 8). 28. constant loop current - the constant loop current is calculated using the following equation: i l = 1000/r lim = v tr /600 (reference figure 10). 29. ground key detector - (trigger) ground the ring pin through a 2.5k ? resistor and verify that gkd goes low. (reset) disconnect the ring pin and verify that gkd goes high. (hysteresis) compare difference between trigger and reset. 30. electrical test - not tested in production at -40c. circuit operation and design information the unislic14 family of slics are voltage feed current sense s ubscriber l ine i nterface c ircuits (slic). for short loop applications, the voltage between the tip and ring terminals varies to maintain a constant loop current. for long loop applications, the voltage between the tip and ring terminals are relatively const ant and the loop current varies in proportion to the load. the tip and ring voltages for various loop resistances are shown in figure 13. the tip voltage remains relatively constant as the ring voltage moves to limit the loop current for short loops. the loop current for various loop resistances are shown in figure 14. for short loops, the loop current is limited to the programmed current limit, set by rilim. for long loop applications, the loop current varies in accordance with ohms law for the given tip to ring voltage and the loop resistance. . the following discussion separates the slic?s operation into its dc and ac paths, then follows up with additional circuit and design information. dc feed curve the dc feed curve for the unislic14 family is user programmable. the user defines the on hook and off hook overhead voltages (including the overhead voltage for off hook pulse metering if applicable), the maximum and minimum loop current limits, the switch hook detect threshold and the battery voltag e. from these requirements, the dc feed curve is customized for optimum operation in any given application. an excel spread sheet to calculate the external components can be downloaded off our web site www.intersil.com/telecom/unislic14.xls. figure 13. tip and ring voltages vs loop resistance tip and ring voltages (v) loop resistance ( ? ) 0 -5 -10 -15 -20 -25 -30 -35 -50 -40 -45 200 600 1000 1400 1800 2000 4k 10k 6k 8k constant loop current region vbh = -48v rd = 41.2k ? roh = 38.3k ? rdc_rac = 19.6k ? rilim = 33.2k ? constant tip to ring voltage region -44.5v -2.5v tip ring figure 14. loop current vs loop resistance loop current (ma) 0 loop resistance ( ? ) 200 600 1k 1.4k 1.8k 2.2k 2.6k 3.8k 3.0k 3.4k 35 30 25 20 15 10 5 constant loop current region vbh = -48v rd = 41.2k ? roh = 38.3k ? rdc_rac = 19.6k ? rilim = 33.2k ? constant tip to ring voltage region HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
15 on hook overhead voltage the on hook overhead voltage at the load (v oh (on) at load) is independent of the v bh battery voltage. once set, the on hook voltage remains constant as the v bh battery voltage changes. the on hook voltage also remains constant over temperature and line leakages up to 0.6 times the switch hook detect threshold (i shd ). the maximum loop current for a constant on hook overhead voltage is defined as ish-. the on hook overhead voltage, required for a given signal level at the load, must take into account the ac voltage drop across the 2 external protection resistors (r p ) and the 2 internal sense resistors (r s ) as shown in figure 16. the ac on hook overload voltage is calculated using equation 1. where v oh(on) at load = on hook overhead voltage at load v sp(on) = required on hook transmission for speech r p = protection resistors (typically 30 ? ) r s = internal sense resistors (40 ? ) z l = ac load impedance for (600 ? ) 1.5v = additional on hook overhead voltage requirement to account for any process and temperature variations in the performance of the slic, 1.5v is added to the overhead voltage requirement for the on hook case in equation 1 and 2.0v for the off hook case in equation 3. note the 2.5v overhead is automatically generated in the slic and is not part of the external overhead programming. ? internal overhead voltage automatically generated by the slic. figure 15. unislic14 dc feed curve vbh 2.5v ? voh(off) at load ish- iloop(min) iloop(max) 60k ? slope r l o o p ( m a x ) slic self programming tip to ring absol ute voltage (v) loop current (ma) ioh constant current region r sat voh(on) at load i shd v bh v oh(on) 2.5v on hook ish- tip to ring voltage loop current dc feed curve overhead ish- = i shd (0.6) i shd (eq. 1 oh on () at load v sp on () 1 2r p 2r s + z l ----------------------------- - + ?? ?? ?? 1.5v + = figure 16. overhead voltage of the tip and ring amplifiers tip and ring internal sense external protection resistor 2r p 2r s amplifiers overhead voltage resistors where: z l required v oh (on, off) v zl is the required on hook or offhook transmission delivered to the load. (load) unislic14 v zl v oh on off , () 2r p 2r s + z l ----------------------------- - ?? ?? ?? v zl = HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
16 off hook overhead voltage the off hook overhead voltage v oh (off) at load is also independent of the v bh battery voltage and remains constant over temperature. the required off hook overhead voltage is the sum of the ac and dc voltage drops across the internal sense resistors (r s) , the protection resistors (r p ), the required (peak) off hook voltage for speech (v sp(off) ) and the required (peak) off hook voltage for the pulse metering (v pm(off) ), if applicable. the off hook overhead voltage is defined in equation 2 and calculated using equation 3. where: v oh(off) at load = off hook overhead voltage at load v oh (r sense ) = required overhead for the dc voltage drop across sense resistors (2r s x iloop (max) ) v sp(off) = required (peak) off hook ac voltage for speech v pm(off) = required (peak) off hook ac voltage for pulse metering where: 80 = 2r s + 2r int (reference figure 17) z pm = pulse metering load impedance (typically 200 ? ). 2.0v = additional off hook overhead voltage requirement r sat resistance calculation the r sat resistance of the dc feed curve is used to determine the value of the rdc_rac resistor (equation 6). the value of this resistor ha s an effect on both the on hook and off hook overheads. in most applications the off hook condition will dominate the overhead requirements. therefore, we?ll start by calculating the r sat value for the off hook conditions and then verify that the on hook conditions are also satisfied. when considering the off hook condition, r sat is equal to v oh(off) at load divided by iloop (min) (equation 4). for the given system requirements (recommended application circuit in back of data sheet): iloop (min) = 20ma, iloop (max) = 30ma, v sp(off) = 3.2v peak , v spm(off) = 0v peak , v oh(off) at load = 8.34v the value of r sat(off) is equal to 417 ? as calculated in equation 4. before using this r sat value, to calculate the rdc_rac resistor, we need to verify that the on hook requirements will also be met. the on hook overhead voltage calculated with the off hook r sat (r sat(off) ), is given in equation 5 and equals 3.0v. the on hook overhead calculated with equation 1 equals 2.85v for the given system requirements (recommended application circuit in back of data sheet): switch hook detect threshold = 12ma, ish- = (0.6)12ma = 7.2ma, v sp(on) = 0.775v rms thus, the on hook overhead requirements of 2.85v will be met if we use the r sat(off) value. if the on hook overhead requirement is not met, then we need to use the r sat(on) value to determine the rdc_rac resistor value. the external saturation guard resistor rdc_rac is equal to 50 times r sat . in the example above r sat would equal 417 ? and rdc_rac would then equal to 20.85k ? (closest standard value is 21k ? ). the switch hook detect threshol d current is set by resistor r d and is calculated using equation 7. for the above v bh v sat v oh(off) 2.5v off hook tip to ring voltage loop current i loop(min) dc feed curve over head (eq. 2) v oh off () at load v oh rsense () v sp off () v pm off () ++ = (eq. 3) v oh(off) at load 80 i loop max () v sp off () 1 2r p 2r s + z l ----------------------------- - + ?? ?? ?? + = + v pm off () 1 2r p 2r s + z pm ----------------------------- - + ?? ?? ?? 2.0v + v bh v sat v oh(off) 2.5v tip to ring voltage loop current i loop(min) v oh(off) at load i loop(min) r sat r sat dc feed curve r sat(off) = v oh(off) at load i loop(min) --------------------------------------- - 8.34v 20ma ---------------- 417 ? == (eq. 4) v oh(on) at load ish- (min) r sat v bh v sat v oh(on) 2.5v ish-(min) loop current dc feed curve tip to ring voltage r sat on () 2.85v 7.2ma ----------------- - 395 ? == r sat v oh on () ish- () r sat off () () = (eq. 5) v oh on () 7.2ma 417 ? = v oh on () 3.0v = rdc_rac = 50 x r sat (eq. 6) HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
17 example r d is calculated to be 41.6k ? (500/12ma). the next closest standard value is 41.2k ?. the true value of ish-, for the selected value of r d is given by equation 8: for the example above, ish- equals 7.28ma (500 x 0.6/ 41.2k). verify that the value of ish- is above the suspected line leakage of the application. the unislic family will provide a constant on hook voltage level for leakage currents up to this value of line leakage. the r oh resistor, which is used to set the offhook overhead voltage, is calculated using equations 9 and 10. i oh is defined as the difference between the i loop(min) and ish-. substituting equation 8 for ish- into equation 9 and solving for r oh defines r oh in terms of i loop(min) and r d . equation 10 can be used to determine the actual ish- value resulting from the r d resistor selected. the value of r d should be the next standard value that is lower than that calculated. this will insure meeting the i loop(min) requirement. roh for the above example equals 39.1k ?. the current limit is set by a single resistor and is calculated using equation 11. the maximum loop resistance is calculated using equation 12. the resistance of the protection resistors (2r p ) is subtracted out to obtain the maximum loop length to meet the required off hook overhead voltage. if r loop(max) meets the loop length requirements you are done. if the loop length needs to be longer, then consider adjusting one of the following: 1) the shd threshold, 2) minimum loop current requirement or 3) the on and off hook signal levels. slic in the active mode figure 17 shows a simplified ac transmission model. circuit analysis yields the following design equations: substitute equation 14 into equation 15 substitute equation 16 into equation 17 substitute equation 18 into equation 19 substituting -v tr /z l into equation 20 for i m and rearranging to solve for v tr results in equation 21 where: v rx = the input voltage at the vrx pin. v a = an internal node voltage that is a function of the loop current detector and the im pedance matching networks. i x = internal current in the slic that is the difference between the input receive current and the feedback current. i m = the ac metallic current. r p = a protection resistor (typical 30 ? ). z t = an external resistor/network for matching the line impedance. v tx = the tip to ring voltage at th e output pins of the slic. r d = 500 i shd ------------ (eq. 7) ish- = 500 r d --------- - (0.6) (eq. 8) v bh v sat v oh(off) 2.5v off hook tip to ring voltage loop current i loop(min) dc feed curve ish- i oh over head r oh 500 i oh --------- - 500 i loop(min) - ish- -------------------------------------------- == (eq. 9) r oh = r d 500 r d i loop(min) - 500(.6) ----------------------------------------------------------- - (eq. 10) r lim = 1000 i loop(max) ----------------------------- (eq. 11) v bh v sat v oh(off) 2.5v tip to ring voltage loop current i loop(min) dc feed curve r l o o p ( m a x ) r loop(max) = v bh v sat 2v v oh off () ++ [] ? i loop(min) ------------------------------------------------------------------------------- -2r p (eq. 12) v a = i m 2r s 1 80k --------- - 200 z tr 2r p ? () 5 (eq. 13) v a i m 2 ------- z tr 2r p ? () = (eq. 14) v rx 500k ------------ - - v a 500k ------------ - = i x node equation (eq. 15) i x v rx 500k ------------ - - i m z tr 2r p ? () 1000k ----------------------------------------- = (eq. 16) i x 500k - v tx + i x 500k = 0 loop equation (eq. 17) v tx 2v rx i m z tr 2r p ? () ? = (eq. 18) v tr -i m 2r p + v tx = 0 loop equation (eq. 19) v tr i m z tr 2v rx ? = (eq. 20) v tr 1 z tr z l ---------- - + ?? ?? ?? 2 ? v rx = (eq. 21) HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
18 v tr = the tip to ring voltage including the voltage across the protection resistors. z l = the line impedance. z tr = the input impedance of the slic including the protection resistors. (ac) 4-wire to 2-wire gain the 4-wire to 2-wire gain is equal to v tr /v rx . from equation 21 and the relationship z t = 200(z tr -2r p ). notice that the phase of the 4-wi re to 2-wire signal is 180out of phase with the input signal. (ac) 2-wire to 4-wire gain the 2-wire to 4-wire gain is equal to v tx /e g with v rx = 0 from equation 18 with v rx = 0 substituting equation 24 into equation 23 and simplifying. by design, vtx = -vtx, therefore a more useful form of the equat ion is rewritten in terms of v tx /v tr . a voltage divider equation is written to convert from e g to v tr as shown in equation 27. rearranging equation 27 in terms of e g , and substituting into equation 26 results in an equation for 2-wire to 4-wire gain that?s a function of the synthesized input impedance of the slic (z tr ) and the protection resistors (r p ). notice that the phase of the 2- wire to 4-wire signal is in phase with the input signal. (ac) 4-wire to 4-wire gain the 4-wire to 4-wire gain is equal to v tx /v rx , e g = 0. from equation 18. substituting -v tr /z l into equation 29 for i m results in equation 30. g 4-2 = v tr v rx ----------- = -2 z l z l + z tr ------------------------- 2 z l z l z t 200 --------- - 2r p + ?? ?? + ---------------------------------------------- ? = (eq. 22) v tx v rx tip ring z tr v tr e g v tx i m v tx unislic14 r p r p + - + - + - - + v rx + - i m z l figure 17. simplified ac transmission circuit + - 500k r s + - 500k r s z t 500k 500k 500k 500k ptg + - i x v a = i m (z tr -2r p ) i x i x + - i x + - 5 + - + - i m + - 20 ? 20 ? 1/80k = 200 (z tr - 2r p ) a = 1 i x 2 r int 20 ? r int 20 ? e ? g z l i m 2r p i m v tx ? + + 0 = loop equation (eq. 23) v tx i m z tr 2r p ? () ? = (eq. 24) e g i m z l z tr + () = (eq. 25) g 2-4 = v tx e g ---------- = i m z tr 2r p ? () i m z l z tr + () --------------------------------------- - z tr 2r p ? () z l z tr + () --------------------------------- = (eq. 26) v tr = z tr z tr z l + ----------------------- - ?? ?? ?? e g (eq. 27) g 2-4 = v tx v tr ---------- - = z tr - 2r p z tr ----------------------------- (eq. 28) v tx v ? tx 2 ? v rx i m z tr 2r p ? () + == (eq. 29) v tx 2 ? v rx v tr z tr 2r p ? () z l --------------------------------------------- ? = (eq. 30) HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
19 substituting equation 21 for v tr in equation 30 and simplifying results in equation 31. (ac) 2-wire impedance the ac 2-wire impedance (z tr ) is the impedance looking into the slic, including the fuse resistors. the formula to calculate the proper z t for matching the 2-wire impedance is shown in equation 32. equation 32 can now be used to match the slic?s impedance to any known line impedance (z tr ). example: calculate z t to make z tr = 600 ? in series with 2.16 f. r p = 30 ? . z t = 108k ? in series with 0.0108 f. note: some impedance models, with a series capacitor, will cause the op-amp feedback to behave as an open circuit dc. a resistor with a value of about 10 times the reactance of the z t capacitor (2.16 f/200 = 10.8nf) at the low frequency of interest (200hz for example) can be placed in parallel with the capacitor in order to solve the problem (736k ? for a 10.8nf capacitor). calculating tip and ring voltages the on hook tip to ground voltage is calculated using equation 34. the minus 1.0 volt results from the slic self programming. ish- is the maximum loop current for a constant on hook over head voltage (ish- = i shd (0.6)) and the value of r sat(off) is calculated in equation 4. on hook tip voltage the off hook tip to ground voltage is calculated using equation 35. i loop(min) is the minimum loop current allowed by the design and the value of r sat(off) is calculated in equation 4. off hook tip voltage the on hook ring to ground voltage is calculated using equation 36. the 1.5 volt results from the slic self programming. ish- is the maximum loop current for a constant on hook overhead voltage (ish- = i shd (0.6)) and the value of r sat(off) is calculated in equation 4. on hook ring voltage the calculation of the ring voltage with respect to ground in the off hook condition is d ependent upon whether the slic is in current limit or not. the off hook ring to ground voltage (in current limit) is calculated using equation 37. i lim is the programmed loop current limit and r l is the load resistance across tip and ring. the minus 0.2v is a correction factor for the 60k ? slope in figure 15. off hook ring voltage in current limit the off hook ring to ground voltage (not in current limit) is calculated using equation 38. the 1.5v results from the slic self programming. i loop(min) is the minimum loop current allowed by the design and the value of r sat(off) is calculated in equation 4. off hook ring voltage not in current limit layout considerations systems with dual supplies (v bh and v bl ) if the v bl supply is not derived from the v bh supply, it is recommended that an additional diode be placed in series with the v bh supply. the orientation of this diode is anode on pin 8 of the device and cat hode to the external supply. this external diode will inhibit large currents and potential damage to the slic, in the event the v bh supply is shorted to gnd. if v bl is derived from v bh then this diode is not required. suggested (not re quired) supply sequence v bh - v bl - v cc . floating the ptg pin the ptg pin is a high impedance pin (500k ? ) that is used to program the 2-wire to 4-wire gain to either 0db or -6db. if 0db is required, it is necessary to float the ptg pin. the pc board interconnect should be as short as possible to minimize stray capacitance on th is pin. stray capacitance on this pin forms a low pass filter and will cause the 2-wire to 4-wire gain to roll off at the higher frequencies. if a 2-wire to 4-wire gain of -6db is required, the ptg pin should be grounded as close to the device as possible. g 44 ? v tx v rx ----------- 2 ? z l + 2r p z l z tr + ------------------------ ?? ?? ?? == (eq. 31) z t 200 z tr 2r p ? () ? = (eq. 32) z t 200 600 1 j 2.16x10 6 ? ----------------------------------- 2 () 30 () ? + ?? ?? ?? = (eq. 33) v tip onhook () 1.0v ? ish- () ? r satoff 2 ---------------------- ?? ?? + = (eq. 34) v tip offhook () 1v ? i loop min () () r sat off () 2 -------------------------- ? = (eq. 35) i loop max () r p ? v ring onhook () v bh 1.5v ish () r sat off () 2 -------------------------- ?? ?? ++ = (eq. 36) v ring cl () v tip offhook () i loop max () r l ? 0.2v ? = (eq. 37) v ring ncl () v bh 1.5v i loop min () () r sat off () 2 -------------------------- ?? ?? ++ = (eq. 38) i loop min () r p ? HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
20 spm pin for optimum performance, t he pc board interconnect the spm pin should be as short as possible. if pulses metering is not being used, then this pin should be grounded as close to the device pin as possible. rlim pin the current limiting resistor r lim needs to be as close to the rlim pin as possible. layout of the 2-wire impedance matching resistor z t proper connection to the zt pin is to have the external z t network as close to the device pin as possible. the zt pin is a high impedanc e pin that is used to set the proper feedback for matching the impedance of the 2-wire side. this will eliminate circuit board capacitance on this pin to maintain the 2-wire return loss across frequency. digital logic inputs table 1 is the logic truth table for the 3v to 5v logic input pins. a combination of the control pins c3, c2 and c1 select 1 of the possible 6 operating st ates. the 8th state listed is thermal shutdown. thermal shutdown protection is invoked if a fault condition on the tip or ring causes the junction temperature of the die to e xceed 175c. a description of each operating state and t he control logic follows: open circuit state (c3 = 0, c2 = 0, c1 = 0) in this state, the tip and ring outputs are in a high impedance condition (>1m ? ). no supervisory functions are available and shd and gkd outputs are at a ttl high level. 4-wire loopback testing can be performed in this state. with the ptg pin floating, the signal on the v tx output is 180 o out of phase and approximately 2 times the v rx input signal. if the ptg pin is grounded, then the amplitude will be approximately the same as its input and 180 o out of phase. ringing state (c3 = 0, c2 = 0, c1 = 1) in this state, the output of the ring relay driver pin (rrly) goes low (energizing the ring relay to connect the ringing signal to the phone) if either of the following two conditions are satisfied: (1) the rsync_rev pin is grounded through a resistor - this connection enables the rrly pin to go low the instant the ringing state is invoked, without any regard for the ringing voltage (90v rms -120v rms ) across the relay contacts. the resistor (34.8k ? to 70k ? ) is required to limit the current into the rsync_rev pin. (2) a ring sync pulse is applied to the rsync_rev pin - this connection enables the rrly pin to go low at the command of a ring sync pulse. a ring sync pulse should go table 1. detector states state c3 c2 c1 slic operating state active detector output shd gkd _ lvm 0 0 0 0 open circuit state 4 wire loopback test capability high high 1 0 0 1 ringing state (previous state cannot be reverse active state) ring trip detector high 2 0 1 0 forward active state loop current detector ground key detector 3 0 1 1 test active state requires previous state to be in the forward active state to determine the on hook or off hook status of the line. on hook loopback detector low ground key detector high off hook loop current detector low line voltage detector 4 1 0 0 tip open - ground start state ground key detector 5 1 0 1 reserved reserved n/a n/a 6 1 1 0 reverse active state loop current detector ground key detector 7 1 1 1 test reversal active state requires previous state to be in the reverse active state to determine the on hook or off hook status of the line. on hook loop current detector high off hook loop current detector low line voltage detector 8 x x x thermal shutdown low low HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
21 low at zero voltage crossing of the ring signal. this pulse should have a rise and fall time <400 s and a minimum pulse width of 2ms. zero ring current detection is performed automatically inside the slic. this feature de-energizes the ring relay slightly before zero current occurs to partially compensate for the delay in the opening of the relay. the shd output will go low when the subscriber goes off hook. once shd is activated, an internal latch will prohibit the re-ringing of the line until the ringing code is removed and then reapplied. the state prior to ringing the phone, can not be the reverse active state. in the reverse ac tive state the polarity of the voltage on the crt_rev_lvm capacitor, will make it appear as if the subscriber is off hook. this subsequently will activate an internal latch prohibiting the ringing of the line. the gkd _lvm output is disabled (ttl high level) during the ringing state. reference the section titled ?ringing the phone? for more information. forward active state (c3 = 0, c2 = 1, c1 = 0) in this state, the slic is fully functional. the tip voltage is more positive than the ring voltage. th e tip and ring output voltages are an unbalanced dc feed, reference figure 13. both shd and gkd supervisory functions are active. reference the section titled ?dc feed curve? for more information. test active state (c3 = 0, c2 = 1, c1 = 1) proper operation of the test active state requires the previous state be the forward active state to determine the on hook or off hook status of the line. in this state, the slic can perform two different tests. if the subscriber is on hook when the state is entered, a loopback test is performed by switching an internal 600 ? resistor between tip and ring. the current flows through the internal 600 ? is unidirectional via blocking diodes. (cannot be used in reverse.) when the lo opback current flows, the shd output will go low and remain there until the state is exited. this is intended to be a short test since the ability to detect subscriber off hook is lost duri ng loopback testing. reference the section titled ?loopback tests? for more information. if the subscriber is off hook when the state is entered, a line voltage measurement test is performed. the output of the gkd _lvm pin is a pulse train. the pulse width of the active low portion of the signal is proportional to the voltage across the tip and ring pins. if the loop length is such that the slic is operating in constant current, the tip to ring voltage can be used to determine the length of the line under test. the longer the line, the larger the tip to ring voltage and the wider the pulse. this relationship can determine the length of the line for setting gains in the system. reference the section titled ?operation of l ine v oltage m easurement? for more information. tip open state (c3 = 1, c2 = 0, c1 = 0) in this state, the tip output is in a high impedance state (>250k ?) and the ring output is capabl e of full operation, i.e. has full longitudinal current capability. the tip open/ground start state is used to inte rface to a pbx incoming 2-wire trunk line. when a ground is applied through a resistor to the ring lead, this current is detected and presented as a ttl logic low on the shd and gkd _lvm output pins. reserved (c3 = 1, c2 = 0, c1 = 1) this state is undefined and reserved for future use. reverse active state (c3 = 1, c2 = 1, c1 = 0) in this state, the slic is fully functional. the ring voltage is more positive than the tip voltage. the tip and ring output voltages are an unbalanced dc feed, reference figure 13. the polarity reversal time is determined by the rc time constant of the rsync_rev resistor and the crt_rev_lvm capacitor. capacitor crt_rev_lvm performs three different functions : ring trip filtering, polarity reversal time and line voltage measurement. it is recommended that programming of the reversal time be accomplished by changing the value of rsync_rev resistor (see figure 18). the value of rsync_rev resistor is limited between 34.8k (10ms) and 73.2k (21ms). equation 39 gives the formula for programming the reversal time. both shd and gkd supervisory functions are active. reference the section titled ?polarity reversal? for more information. test reversal active state (c3 = 1, c2 = 1, c1 = 1) proper operation of the test re versal active state requires the previous state be the reverse active state to determine the on hook or off hook status of the line. if the subscriber is on hook when the state is entered, the slic?s tip and ring voltages are the same as the reverse active state. the shd output will go low when the subscriber goes off hook and the gkd _lvm output is disabled (ttl level high). (note: operation is the same as the reverse active state with the gk d_lvm output disabled.) if the subscriber is off hook when the state is entered, a line voltage measurement test is performed. the output of the gkd _lvm pin is a pulse train. the pulse width of the active low portion of the signal is proportional to the voltage across the tip and ring pins. if the loop length is such that the slic is operating in constant curr ent mode, the tip to ring voltage can be used to determine the length of the line under test. the longer the line, the larger the tip to ring voltage and the wider the pulse. this relationship can determine the length of the line for setting gains in the system. reference the section titled ?operation of l ine v oltage m easurement? for more information. rsync rev ? 3.47k ? reversaltime ms () = (eq. 39) HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
22 thermal shutdown the unislic14?s thermal shutdown protection is invoked if a fault condition causes the juncti on temperature of the die to exceed about 175c. once the thermal limit is exceeded, both detector outputs go low (shd and gkd _lvm ) and one of two things can happen. for marginal faults where loop current is flowing during the time of the over-temperature condition, foldback loop current limiting reduces the loop current by reducing the tip to ring voltage. an equilibrium condition will exist that maintains the junction temperature at about 175c until the fault condition is removed. for short circuit faults (tip or ring to ground, or to a supply, etc.) that result in an ov er-temperature condition, the foldback current limiting will try to maintain an equilibrium at about 175c. if the junction temperature keeps rising, the device will thermally shutdown and disconnect tip and ring until the junction te mperature falls to approximately 150c. supervisory functions switch hook detect threshold the switch hook detect threshold is programmed with a single external resistor (r d ). the output of the shd pin goes low when an off hook condition is detected. ground key detect threshold the ground key detect threshold is set internally and is not user programmable. ringing the phone the unislic14 family handles all the popular ringing formats with high or low side ring trip detection. high side detection is possible because of the high common mode range on the ring signal detect input pins (dt, dr). to minimize power drain from the ring generator, when the phone is not being rung, the se nse resistors are typically 2m ? . this reduces the current draw from the ring generator to just a few microamps. when the subscriber goes off hook during ringing, the unislic14 family automatically releases the ring relay and dc feed is applied to the loop. the unislic14 family has very low power dissipation in the on hook active mode. this enables the slic (during the ring cadence) to be powered up in the active state, avoiding unnecessary powering up and down of the slic. the control logic is designed to facilitate easy implementation of the ring cadence, requiring only one bit change to go from active to ringing and back again. dt, dr and rrly inputs ring trip detection will occur when the dr pin goes more positive than dt by approximately 4v. the ring relay driver pin, rrly, has an internal clamp between it?s output and ground. this eliminates the need to place an external snubber diode across the ring relay. reducing impulse noise during ringing with an increase in digital data lines being installed next to analog lines, the threat from impulse noise on analog lines is increasing. impulse noise can cause large blocks of high speed data to be lost, defeating most error correcting techniques. the unislic14 family has the capability to reduce impulse noise by closing the ring relay at zero voltage and opening the ring relay at zero current. closing the ring relay at zero voltage closing the ring relay at zero voltage is accomplished by providing a ring sync pulse to the rsync_rev pin. the ring sync pulse is synchro nized to go low at the zero voltage crossing of the ring signal. the resistor r1 in figure 18 limits the current into the rsync_rev pin. if a particular polarity reversal time is required, then make r1 equal to the calculated value in equation 39. if a specific polarity reversal time is not desired, r1 equal to 50k ? is suggested. the rsync_rev pin is designed to allow the ring sync pulse to be present at all times. there is no need to gate the ring sync pulse on and off. the logic control for the rsync_rev pin cannot be an open collector. it must be high (push-pull logic output sta ge / pull up resistor to vcc), low or being clocked by the ring sync pulse. when the rsync_rev pin is high the ring relay pin is disabled. when the rsync_rev pin is low the ring relay pin is activated the instant the logic code for ringing is applied. opening the ring relay at zero current the ring relay is automatically opened at zero current by the slic. the slic logic requires zero ringing current in the loop and either a valid switch hook detect (shd ) or a change in the operating mode (cadence of the ringing signal) to release the ring relay. if the subscriber goes off hook during ringing, the shd output will go low. an internal latch will sense shd is low and disable the ring relay at zero ringing current. this prevents the ring signal from being reapplied to the line. to ring the line again, the slic must toggle between logic states. (note: the previous state can not be the reverse active state. in the revers e state, the voltage on the figure 18. reducing impulse noise using the rsync_rev pin and setting the polarity reversal time rsync_rev 24 r 1 input for the ring sync pulse unislic14 50k ? 5v 0v HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
23 crt_rev_lvm capacitor will activate an internal latch prohibiting the ringing of the line. figure 19 shows the sequence of events from ringing the phone to ring trip. the ring relay turns on when both the ringing code and ring sync pulse are present (a). shd is high at this point. when the subscriber goes off hook the shd pin goes low and stays low until the ringing control code is removed (b). this prevents the shd output from pulsing after ring trip occurs. at the next zero current crossing of the ring signal, ring trip occurs and the ring relay releases the line to allow loop current to flow in the loop (c). operation of line voltage measurement a few of the slics in the un islic14 family feature line voltage measurement (lvm) capability. this feature provides a pulse on the gkd _lvm output pin that is proportional to the loop volt age. knowing the loop voltage and thus the loop length, other basic cable characteristics such as attenuation and capacitance can be inferred. decisions can be made about gain switching in the codec to overcome line losses and verification of the 2-wire circuit integrity. the lvm function can only be activated in the off hook condition in either the forward or reverse operating states. the lvm uses the ring signal supplied to the slic as a timebase generator. the loop resistance is determined by monitoring the pulse width of the output signal on the gkd _lvm pin. the output signal on the gkd _lvm pin is a square wave for which the average duration of the low state is proportional to the average voltage between the tip and ring terminals. the loop resistance is determined by the tip to ring voltage and the constant loop current. reference figure 20. although the logic state changes to the test active state when performing this test, the slic is still powered up in the active state (forward or reverse) and the subscriber is unaware the measurement is being taken. polarity reversal most of the slics in the unislic14 family feature full polarity reversal. full polarity reversal means that the slic can: transmit, determine the st atus of the line (on hook and off hook) and provide ?silent? polarity reversal. the value of rsync_rev resistor is limited between 34.8k (10ms) and 73.2k (21ms). reference equation 39 to program the polarity reversal time. transhybrid balance if a low cost codec is chosen that does not have a transmit op-amp, the unislic14 family of slics can solve this problem without the need for an additional op-amp. the solution is to use the p rogrammable t ransmit g ain pin (ptg) as an input for the receive signal (v rx ). in theory, when the ptg pin is connected to a divider network (r1 and r2 figure 21) and the value of r1 and r2 is much less than the internal 500k ? resistors, two things happen. first the transmit gain from v rx to v tx is reduced by half. this is the result of shorting out the bottom 500k ? resistor with the much smaller external resistor. and sec ond, the input signal from v rx is also decreased by the voltage divider r1 and r2. transhybrid balance occurs when these two, equal but opposite in phase, signals are cancelled at the input to the output buffer. the calculation of the value of r2, once r1 is selected, is effected by the line feed resistors. eq. 40 can be used to calculate the value of r2. where : z l = line impedance, z tr = input impedance of slic including the protection resistor, and rp = protection resitors (typical 30 ? ). figure 19. ringing sequence off on off relay driver ringing current in line shd output ringing code applied ring sync pulse ringing voltage (a) (b) (c) figure 20. operation of the line voltage measurement circuit tip ring dt dr ring gen gkd _lvm ring gen freq pulse width proportional to loop length pulse loop length width unislic14 r 2 r 1 ii500k 1.02 -------------------------- z l + z tr z l + 2zr p ----------------------------- - ?? ?? ?? r 1 ii500k 1.02 -------------------------- ? = (eq. 40) HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
24 loopback tests 4-wire loopback test this feature can be very useful in the testing of line cards during the manufacturing process and in field use. the test is unobtrusive, allowing it to be used in live systems. reference figure 22. most systems do not provide 4- wire loopback test capability because of costly relays needed to switch in external loads. all the slics in the unislic 14 family can easily provide this function when configured in the open circuit logic state. with the ptg pin floating, the signal on the v tx output is 180 o out of phase and approximately 2 times the v rx input signal. if the ptg pin is grounded, then the amplitude will be approximately the same as the input signal and 180 o out of phase. 2-wire loopback test most of the slics in the unis lic14 family feature 2-wire loopback testing. this loopback function is only activated when the subscriber is on hook and the logic command to the slic is in the test active state. (note: if the subscriber is off hook and in the test active state, the function performed is the line voltage measurement.) during the 2-wire loopback test, a 2k ? internal resistor is switched across the tip and ring terminals of the slic. this allows the shd function and the 4-wire to 4-wire ac transmission, right up to the subscriber loop, to be tested. together with the 4-wire loopback test in the open circuit logic state, this 2-wire loopback test allows the complete network (including slic) to be tested up to the subscriber loop. pulse metering the hc55121, hc55142, hc35143, hc55150 and the hc55151 are designed to support pulse metering. they offer solutions to the following pulse metering design issues: 1) providing adequate signal gain and current drive to the subscriber metering equipment to overcome the attenuation of this (12khz, 16khz) out of band signal. 2) attenuating the pulse mete ring transhybrid signal without severely attenuating the voice band signal to avoid clipping in the codec/filter. 3) tailoring the overload levels in the slic to avoid clipping of the combined voiceband and pulse metering signal. 4) having the provision of silent polarity reversal as a backup in the case where the loop attenuates the out of band signal too much for it to be detected by the subscriber?s metering equipment. adequate signal gain adequate signal gain and current drive to the subscriber?s metering equipment is made easier by the network shown in figure 23. the pulse metering signal is supplied to a dedicated high impedance input pin called spm. the circuit in figure 23 shows the connection of a network that sets the 2-wire impedance (z tr ), at the pulse metering frequencies, to be approximately 200 ? . if the line impedance (z l ) is equal to 200 ? at the pulse metering frequencies, then the 4- wire to 2-wire gain (v tr / spm) is equal 4. thereby lowering the input signal requirements of the pulse metering signal. note: the automatic pulse metering 2-wire impedance matching is independent of the programmed 2-wire impedance matching at voiceband frequencies. calculation of the pulse metering gain is achieved by replacing v rx /500k in equation 15 with spm/125k and following the same process through to equation 21. the unislic14 sets the 2-wire input impedance of the slic (z tr ), including the protection resistors, equal to 200 ? . the results are shown in equation 41. avoiding clipping in the codec/filter the amplitude of the returning pulse metering signal is often very large and could easily over drive the input to the codec/filter. by using the same method discussed in section ?transhybrid balance?, most if not all of the pulse metering signal can be cancel ed out before it reaches the input to the codec/filter. th is connection is shown in figure 23. figure 21. transhybrid balance using the ptg pin v tx v rx v tx - + v rx + - 500k 500k 500k ptg + - i x 5 a = 1 i x r1 r2 500k unislic14 figure 22. 4-wire and 2-wire loopback tests v tx v rx tip ring 4-wire loopback unislic14 600 ? dual supply codec/filter internal 2-wire loopback + - ptg a 4-2 = v tr spm ------------- = 8 ? z l z l + z tr ------------------------- 8 200 200 + 200 --------------------------- ? 4 ? == (eq. 41) HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
25 overload levels and s ilent polarity reversal the pulse metering signal and voice are simultaneously transmitted, and therefore require additional overhead to prevent distortion of the sign al. reference section ?off hook overhead voltage? to account for the additional pulse metering signal requirements. most of the slics in the un islic14 family feature full polarity reversal. full polarity reversal means that the slic can: transmit, determine the st atus of the line (on hook and off hook) and provide ?silent? polarity reversal. reference equation 39 to program the polarity reversal time. interface to dual and single supply codecs great care has been taken to mi nimize the number of external components required with the unislic14 family while still providing the maximum flexibilit y. figures 24a, 24b) shows the connection of the unislic14 to both a dual supply codec/filter and a single supply dsp codec/filter. to eliminate the dc blocking capacitors between the slic and the codec/filter when using a dual supply codec/filter, both the receive and transmit leads of the slic are referenced to ground. this leads to a very simple slic to codec/filter interface, as shown in figure 24a. when using a single supply dsp codec/filter the output and input of the code c/filter are no longer referenced to ground. to achieve maximum voltage swing with a single supply, both the output and i nput of the codec/filter are referenced to its own v cc /2 reference. t hus, dc blocking capacitors are once again requir ed. by using the ptg pin of the unislic14 and the externally supplied v cc /2 reference of the codec/filter , one of the dc blocking capacitors can be eliminated (figure 24b). power management the unislic14 family provides two distinct power management capabilities: power sharing and battery selection power sharing power sharing is a method of redistributing the power away from the slic in short loop applications. the total system power is the same, but the die temperature of the slic is much lower. power sharing becomes important if the application has a single battery supply (-48v on hook requirements for faxes and modems) and the possibility of high loop currents (reference figure 25). this technique would prevent the slic from getting too hot and thermally shutting down on short loops. the power dissipation in the slic is the sum of the smaller quiescent supply power and the much larger power that results from the loop current. the power that results from the loop current is the loop current times the voltage across the slic. the power sharing resistor (r ps ) reduces the voltage across the slic, and thereby the on-chip power dissipation. the voltage across the slic is reduced by the voltage drop across r ps . this occurs because r ps is in series with the loop current and the negative supply. figure 23. pulse metering with transhybrid balance v tx v spm v tx - + v ttx + - 125k rb ptg + - i x 5 a = 1 i x ra unislic14 output buffer 150pf c added to bottom of board r added to bottom of board 500k 500k 30.1k figure 24a. figure 24b. figure 24. interface to dual and single supply codecs v tx + - a = 1 v rx unislic14 v out dual supply codec/filter + - 5v gnd -5v v tx 500k ptg + - a = 1 500k v rx unislic14 single supply codec/filter 5v gnd dsp v in v out v ref HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
26 a mathematical veri fication follows: given: v bh = v bl = -48v, loop current = 30ma, r l (load across tip and ring) = 600 ? , quiescent battery power = (48v) (0.8ma) = 38.4mw, qu iescent vcc power = (5v) (2.7ma) = 13.5mw, power sharing resistor = 600 ? . 1. without power sharing, t he on-chip power dissipation would be 952mw (equation 42). 2. with power sharing, the on-chip power dissipation is 412mw (equation 43). a power redistribution of 540mw. on-chip power dissipation without power sharing resistor. on-chip power dissipation with 600 ? power sharing resistor. battery selection battery selection is a technique, for a two battery supply system, where the slic autom atically dive rts the loop current to the most appropriate supply for a given loop length. this results in significant power savings and lowers the total power consumption on short loops. this technique is particularly useful if most of the lines are short, and the on hook condition requires a -48v battery. in figure 26, it can be seen that for long loops the majority of the current comes from the high battery supply (v bh ) and for short loops from the low battery supply (v bl ). pd v bh () 30ma () 38.4mw 13.5mw rl () 30ma () 2 ? ++ = (eq. 42) pd 952mw = pd v bh () 30ma () 38.4mw 13.5mw ++ = (eq. 43) r l () 30ma () 2 ? r ps () 30ma () 2 ? pd 412mw = figure 25. power sharing (single supply systems) v tx v rx unislic14 tip ring v bl v bh -48v -48v on short loops, the majority of current flows out the v bl pin r ps figure 26. battery selecti on (dual supply systems) loop current (ma) 0 35 30 25 20 15 10 5 1000 900 800 600 700 575 550 525 500 475 450 400 350 300 250 200 150 2000 loop resistance ( ? ) 100 40 vbh = -48v vbl = -24v rilim = 33.2k ? v bl v bh v bh v bl pinouts - 28 lead plcc packages HC55120 (28 lead plcc) top view hc55121 (28 lead plcc) top view dr c3 c2 c1 shd cdc dt rrly ptg vtx nc vrx zt ch rsync ilim roh rd agnd gkd v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 bgnd tip vbh vbl ring crt rdc_rac dr c3 c2 c1 shd cdc dt rrly ptg vtx spm vrx zt ch rsync_rev ilim roh rd agnd gkd v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 bgnd tip vbh vbl ring crt_rev rdc_rac HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
27 hc55130 (28 lead plcc) top view hc55140 (28 lead plcc) top view hc55142 (28 lead plcc) top view hc55150 (28 lead plcc) top view pinouts - 28 lead plcc packages (continued) dr c3 c2 c1 shd cdc dt rrly ptg vtx nc vrx zt ch rsync ilim roh rd agnd nc v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 bgnd tip vbh vbl ring crt rdc_rac dr c3 c2 c1 shd cdc dt rrly ptg vtx nc vrx zt ch rsync_rev ilim roh rd agnd gkd _lvm v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 bgnd tip vbh vbl ring crt_rev_ rdc_rac lvm dr c3 c2 c1 shd cdc dt rrly ptg vtx spm vrx zt ch rsync_rev ilim roh rd agnd gkd _lvm v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 bgnd tip vbh vbl ring crt_rev_ rdc_rac lvm dr c3 c2 c1 shd cdc dt rrly ptg vtx spm vrx zt ch rsync_rev ilim roh rd agnd lvm v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 bgnd tip vbh vbl ring crt_rev_ rdc_rac lvm HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
28 pinouts - 32 lead plcc packages hc55131 (32 lead plcc) top view hc55141 (32 lead plcc) top view hc55143 (32 lead plcc) top view hc55151 (32 lead plcc) top view dr c3 c2 c1 shd cdc dt rrly ptg vtx vrx zt ch rsync ilim roh rd agnd nc v cc 1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 30 31 32 bgnd tip vbh vbl ring crt rdc_rac 12 13 c5 c4 29 28 27 26 25 24 23 22 21 nc trly2 trly1 dr c3 c2 c1 shd cdc dt rrly ptg vtx vrx zt ch rsync_rev ilim roh rd agnd gkd _lvm v cc 1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 30 31 32 bgnd tip vbh vbl ring crt_rev_lvm rdc_rac 12 13 c5 c4 29 28 27 26 25 24 23 22 21 nc trly2 trly1 dr c3 c2 c1 shd cdc dt rrly ptg vtx vrx zt ch rsync_rev ilim roh rd agnd gkd _lvm v cc 1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 30 31 32 bgnd tip vbh vbl ring crt_rev_ rdc_rac 12 13 c5 c4 29 28 27 26 25 24 23 22 21 spm trly2 trly1 lvm dr c3 c2 c1 shd cdc dt rrly ptg vtx vrx zt ch rsync_rev ilim roh rd agnd lvm v cc 1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 30 31 32 bgnd tip vbh vbl ring crt_rev_ rdc_rac 12 13 c5 c4 29 28 27 26 25 24 23 22 21 spm trly2 trly1 lvm HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
29 pinouts - 28 lead soic packages HC55120 (28 lead soic) top view hc55121 (28 lead soic) top view hc55130 (28 lead soic) top view hc55140 (28 lead soic) top view zt ptg rrly ch ring bgnd tip vbh vbl rdc_rac cdc dt dr crt agnd nc vrx rsync ilim rd shd c1 c2 c3 gkd vtx roh v cc 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 zt ptg rrly ch ring bgnd tip vbh vbl rdc_rac cdc dt dr crt_rev agnd spm vrx rsync_rev ilim rd shd c1 c2 c3 gkd vtx roh v cc 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 zt ptg rrly ch ring bgnd tip vbh vbl rdc_rac cdc dt dr crt agnd nc vrx rsync ilim rd shd c1 c2 c3 nc vtx roh v cc 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 zt ptg rrly ch ring bgnd tip vbh vbl rdc_rac cdc dt dr crt_rev_lvm agnd nc vrx rsync_rev ilim rd shd c1 c2 c3 gkd _lvm vtx roh v cc 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
30 hc55142 (28 lead soic) top view hc55150 (28 lead soic) top view pinouts - 28 lead soic packages (continued) zt ptg rrly ch ring bgnd tip vbh vbl rdc_rac cdc dt dr crt_rev_lvm agnd spm vrx rsync_rev ilim rd shd c1 c2 c3 gkd _lvm vtx roh v cc 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 zt ptg rrly ch ring bgnd tip vbh vbl rdc_rac cdc dt dr crt_rev_lvm agnd spm vrx rsync_rev ilim rd shd c1 c2 c3 lvm vtx roh v cc 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 pin descriptions 28 pin plcc 32 pin plcc 28 pin soic symbol description 1 1 2 ptg programmable transmit gain - the 2-wire to 4-wire transmission gain is 0db if this pin is left floating and -6.02db if tied to ground. the -6.02db gain option is useful in systems where pulse metering is used. see figure 23. 2 2 3 rrly ring relay driver output - the relay coil may be connected to a maximum of 14v. 3 3 4 ch ac/dc separation capacitor - ch is required to properly process the ac current from the dc loop current. recommended value 0.1 f. 4 4 1 zt 2-wire impedance matching pin - impedance matching of the 2-wire side is accomplished by placing an impedance between the zt pin and ground. see equation 32. 5 5 5 ring connects via protection resistor r p to ring wire of subscriber pair. 6 6 6 bgnd battery ground. 7 7 7 tip connects via protection resistor r p to tip wire of subscriber pair. 888 v bh high battery supply (negative with respect to gnd). 999 v bl low battery supply (negative with respect to gnd, magnitude v bh ). 10 10 10 rdc_rac resistive feed/anti clippi ng - performs anti clipping function on constant current application and sets the slope of the resistive feed curv e for constant voltage applications. 11 11 14 crt_rev _lvm ring trip, soft polarity reversal and line voltage measurement - a capacitor when placed between the crt_rev_lvm pin and +5v performs 3 mutually exclusive functions. when the slic is configured in the ringing mode it provides filtering of the ringing signal to prevent false detect. when the slic is transitioning between the forward active state and reverse active state it provides soft polarity reversal and performs charge storage in the line voltage measurement state. recommended value 0.47 f. 12 12 11 cdc filter capacitor - the cdc capacitor remove s the vf signals from the battery feed control loop. 13 13 12 dt tip side of ring trip detector - ring trip det ection is accomplished by con necting an external network to a detector in the slic with inputs dt and dr. ring trip occurs when the voltage on dt is more negative than the voltage on dr. 14 14 13 dr ring side of ring trip detector - ring tr ip detection is accomplished by connecting an external network to a detector in the slic with inputs dt and dr. ring trip occurs when the voltage on dr is more positive than the voltage on dt. - 15 - c5 activates test relay trly2. ttl compatible logic input. c5 input high, test relay trlt2 low(on). c5 input floating, test relay trly2 hi gh(off). this is due to an internal 100k ? pull down resistor. HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
31 - 16 - c4 activates test relay trly1. ttl compatible logic input. c4 input high, test relay trlt1 low(on). c4 input floating, test relay trly1 hi gh(off). this is due to an internal 100k ? pull down resistor. 15 17 16 c3 ttl compatible logic input. the logic states of c1, c2 and c3 determine the operating states of the slic. reference table 1 for details. 16 18 17 c2 ttl compatible logic input. the logic states of c1, c2 and c3 determine the operating states of the slic. reference table 1 for details. 17 19 18 c1 ttl compatible logic input. the logic states of c1, c2 and c3 determine the operating states of the slic. reference table 1 for details. 18 20 19 shd switch hook detect - active during off hook, ground key and loopback. reference table 1 for details. 19 21 15 gkd_lvm ground key detector and line voltage measurement - reference table 1 for details. 20 22 20 v cc 5v supply. 21 23 21 rd loop current threshold programming pin - a resistor between this pin and ground will determine the trigger level for the loop current detect circuit. see equation 7. 22 24 22 roh off hook overload setting resistor - used to set combined overhead for voice and pulse metering signals. see equation 10. 23 25 23 ilim current limit programming pin - a resistor between this pin and ground will determine the constant current limit of the feed curve. see equation 11. 24 26 24 rsync_rev ring synchronization input and reversal time setting. a resistor between this pin and gnd determines the polarity reversal ti me. synchronization of the closing of the relay at zero voltage is achieved via a ring sync pulse (5 v to 0v) synchronized to the ring signal zero voltage crossing (reference figure 18). 25 27 28 agnd analog ground 26 28 25 vrx receive input - ground referenced 4-wire side. 27 29 26 spm pulse metering signal input. if pulse metering is not used, then this pin should be grounded as close to the device pin as possible. input impedance to ground = 125k ?. 28 30 27 vtx transmit output - ground referenced 4-wire side. - 31 - trly2 test relay driver 2. open collector transistor. internal cl amp between it?s output and ground elimnates the need to place an external snubber diode across test relay driver. trly2 may be connected to maximum of 14v. - 32 - trly1 test relay driver 1. open collector transistor. internal cl amp between it?s output and ground elimnates the need to place an external snubber diode across test relay driver. trly1 may be connected to maximum of 14v. pin descriptions (continued) 28 pin plcc 32 pin plcc 28 pin soic symbol description HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
32 basic application circ uit - voice only 28 lead plcc package tip ring figure 27. unislic14 voice only basic application circuit v tx v rx zt rsync_rev ilim roh rd shd gkd _lvm c1 c2 c3 v cc rrly ch bgnd vbh vbl rdc_rac cdc dr dt crt_rev_lvm c 1 +5v +5v or relay c 2 -24v c 5 -48v r 1 c 3 r p ring tip r p r 2 r 3 vbat ring control logic r 4 r 6 r 7 r 8 r 5 ? r 9 ? r 10 r 11 codec/filter c 4 r 12 u1 u2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 26 28 ptg generator c7 +5v c 6 agnd 25 c 8 c 9 spm 27 +12v d 1 optional ? perform transhybrid balance when using a non-dsp codec. ?? not required for ?? c10 ?? c11 non-dsp codec?s. not required for dsp codec. required for dsp codec?s +- table 2. basic application circuit component list component value tolerance rating u1 - slic unislic14 family n/a n/a u2 - dual asymmetrical transient voltage suppressor tisp1072f3 n/a n/a rp (line feed resistors) 30 ? matched 1% 2.0w r1 (rdc_rac resistor) 21k ? 1% 1/16w r2, r3 2m ? 1% 1/16w r4 (rd resistor) 41.2k ? 1% 1/16w r5 (roh resistor) 38.3k ? 1% 1/16w r6 (rilim resistor) 33.2k ? 1% 1/16w r7 (rsync_rev resistor) 34.8k ? 1% 1/16w r8 (rzt resistor) 107k ? 1% 1/16w r9, r10, r11 20k ? 1% 1/16w r12 400 ? 5% 2w c1 (supply decoupling), c2 0.1 f 20% 10v c5 (supply decoupling) 0.1 f 20% 50v c6 (supply decoupling) 0.1 f 20% 100v c4, c7, c10, c11 0.47 f 20% 10v c3 4.7 f 20% 50v c8, c9 2200pf 20% 100v d1, recommended if the vbl supply is not derived from the vbh supply 1n4004 - - design parameters : maximum on hook voltage = 0.775v rms , maximum off hook voice = 3.2v peak , switch hook threshold = 12ma, loop current limit = 31ma, synthesize device impedance = 540 ? (600 - 60), with 30 ? protection resistors, impedance across tip and ring terminals = 600 ? . where applicable, these component values apply to the basic application circuits for the HC55120, hc55121, hc55130/1, hc55140/1 , hc55142/3 and hc55150/1. pins not shown in the basic a pplication circuit are no connect (nc) pins. HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
33 basic application circ uit - pulse metering 28 lead plcc package figure 28. unislic14 pulse metering basic application circuit v tx vrx zt rsync_rev ilim r oh rd shd gkd _lvm c1 c2 c3 v cc rrly ch vbh vbl rdc_rac cdc dr dt crt_rev_lvm c 1 +5v relay c 2 c 3 r p ring tip r p r 2 r 3 v bat ring control logic r 4 r 6 r 7 r 8 r 5 ? r 9 ? r 10 r 11 codec/filter c 4 r 12 u1 2 3 8 9 11 12 13 14 20 1 4 15 16 17 18 19 21 22 23 24 26 28 ptg agnd spm 12/16khz pulse metering input signal generator r 1 10 c7 +5v -24v c 5 -48v c 6 25 27 tip ring bgnd u2 5 6 7 c 8 c 9 +5v or +12v d 1 optional ?? c10 ?? c11 ? perform transhybrid balance when using a non-dsp codec. ?? not required for non-dsp codec?s. not required for dsp codec. required for dsp codec?s +- table 3. basic application circuit component list component value tolerance rating u1 - slic unislic14 family n/a n/a u2 - dual asymmetrical transient voltage suppressor tisp1072f3 n/a n/a rp (line feed resistors) 30 ? matched 1% 2.0w r1 (rdc_rac resistor) 26.1k ? 1% 1/16w r2, r3 2m ? 1% 1/16w r4 (rd resistor) 41.2k ? 1% 1/16w r5 (roh resistor) 38.3k ? 1% 1/16w r6 (rilim resistor) 33.2k ? 1% 1/16w r7 (rsync_rev resistor) 34.8k ? 1% 1/16w r8 (rzt resistor) 107k ? 1% 1/16w r9, r10, r11 20k ? 1% 1/16w r12 400 ? 5% 2w c1 (supply decoupling), c2 0.1 f 20% 10v c5 (supply decoupling) 0.1 f 20% 50v c6 (supply decoupling) 0.1 f 20% 100v c4, c7, c10, c11 0.47 f 20% 10v c3 4.7 f 20% 50v c8, c9 2200pf 20% 100v d1, recommended if the vbl supply is not derived from the vbh supply 1n4004 - - design parameters : maximum on hook voltage = 0.775v rms , maximum off hook voice = 1.1v peak , maximum simultaneous pulse metering signal = 2.2v rms , switch hook threshold = 12ma, loop current limit = 31ma, synthesize device impedance = 540 ? (600 - 60), with 30 ? protection resistors, impedance across tip and ring terminals = 600 ? . where applicable, these component values apply to the basic application circuits for the HC55120, hc55121, hc55130/1, hc55140/1, hc55142/3 and hc55150/1. pins not shown in the basic application circu it are no connect (nc) pins. HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
34 basic application circ uit - voice only 28 lead soic package figure 29. unislic14 voice only basic application circuit v tx v rx zt rsync_rev ilim r oh rd shd gkd _lvm c1 c2 c3 v cc rrly ch v bh v bl rdc_rac cdc dr dt crt_rev_lvm c 1 +5v relay c 2 r 1 c 3 r p ring tip r p r 2 r 3 v bat ring control logic r 4 r 6 r 7 r 8 r 5 ? r 9 ? r 10 r 11 codec/filter c 4 r 12 u1 1 3 4 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 generator c7 +5v -24v c 5 -48v c 6 agnd 28 tip ring bgnd u2 5 6 7 c 8 c 9 spm 26 +5v or +12v d 1 optional ?? c10 ?? c11 ? perform transhybrid balance when using a non-dsp codec. ?? not required for non-dsp codec?s. not required for dsp codec. required for dsp codec?s +- table 4. basic application circuit component list component value tolerance rating u1 - slic unislic14 family n/a n/a u2 - dual asymmetrical transient voltage suppressor tisp1072f3 n/a n/a rp (line feed resistors) 30 ? matched 1% 2.0w r1 (rdc_rac resistor) 21k ? 1% 1/16w r2, r3 2m ? 1% 1/16w r4 (rd resistor) 41.2k ? 1% 1/16w r5 (roh resistor) 38.3k ? 1% 1/16w r6 (rilim resistor) 33.2k ? 1% 1/16w r7 (rsync_rev resistor) 34.8k ? 1% 1/16w r8 (rzt resistor) 107k ? 1% 1/16w r9, r10, r11 20k ? 1% 1/16w r12 400 ? 5% 2w c1 (supply decoupling), c2 0.1 f 20% 10v c5 (supply decoupling) 0.1 f 20% 50v c6 (supply decoupling) 0.1 f 20% 100v c4, c7, c10, c11 0.47 f 20% 10v c3 4.7 f 20% 50v c8, c9 2200pf 20% 100v d1, recommended if the vbl supply is not derived from the vbh supply 1n4004 - - design parameters : maximum on hook voltage = 0.775v rms , maximum off hook voice = 3.2v peak , switch hook threshold = 12ma, loop current limit = 31ma, synthesize device impedance = 540 ? (600 - 60), with 30 ? protection resistors, impedance across tip and ring terminals = 600 ? . where applicable, these component values apply to the basic application circuits for the HC55120, hc55121, hc55130/1, hc55140/1 , hc55142/3 and hc55150/1. pins not shown in the basic a pplication circuit are no connect (nc) pins. HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151
35 HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mo ld flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. in- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional . if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m28.3 (jedec ms-013-ae issue c ) 28 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.0200 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.6969 0.7125 17.70 18.10 3 e 0.2914 0.2992 7.40 7.60 4 e 0.05 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.01 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n28 287 0 o 8 o 0 o 8 o - rev. 0 12/93
36 HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151 plastic leaded chip carrier packages (plcc) notes: 1. controlling dimension: inch. c onverted millimeter dimensions are not necessarily exact. 2. dimensions and tolerancing per ansi y14.5m-1982. 3. dimensions d1 and e1 do not include mold protrusions. allowable mold protrusion is 0.010 inch (0.25mm) per side. dimensions d1 and e1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. to be measured at seating plane contact point. 5. centerline to be determined where center leads exit plastic body. 6. ?n? is the number of terminal positions. -c- a1 a seating plane 0.020 (0.51) min view ?a? d2/e2 0.025 (0.64) 0.045 (1.14) r 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) tp e e1 0.042 (1.07) 0.048 (1.22) pin (1) identifier c l d1 d 0.020 (0.51) max 3 plcs 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) min 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) min view ?a? typ. 0.004 (0.10) c -c- d2/e2 c l n28.45 (jedec ms-018ab issue a) 28 lead plastic leaded chip carrier package symbol inches millimeters notes min max min max a 0.165 0.180 4.20 4.57 - a1 0.090 0.120 2.29 3.04 - d 0.485 0.495 12.32 12.57 - d1 0.450 0.456 11.43 11.58 3 d2 0.191 0.219 4.86 5.56 4, 5 e 0.485 0.495 12.32 12.57 - e1 0.450 0.456 11.43 11.58 3 e2 0.191 0.219 4.86 5.56 4, 5 n28 286 rev. 2 11/97
37 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com HC55120, hc55121, hc55130, hc55131, hc55140, hc55141, hc55142, hc55143, hc55150, hc55151 plastic leaded chip carrier packages (plcc) a1 a seating plane 0.015 (0.38) min view ?a? d2/e2 0.025 (0.64) 0.045 (1.14) r 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) tp e e1 pin (1) c l d1 d 0.020 (0.51) max 3 plcs 0.026 (0.66) 0.032 (0.81) 0.050 (1.27) min 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) min view ?a? typ. 0.004 (0.10) c -c- d2/e2 c l ne nd identifier (0.12) m ds - b s as 0.042 (1.07) 0.048 (1.22) 0.005 n32.45x55 (jedec ms-016ae issue a) 32 lead plastic leaded chip carrier package symbol inches millimeters notes min max min max a 0.125 0.140 3.18 3.55 - a1 0.060 0.095 1.53 2.41 - d 0.485 0.495 12.32 12.57 - d1 0.447 0.453 11.36 11.50 3 d2 0.188 0.223 4.78 5.66 4, 5 e 0.585 0.595 14.86 15.11 - e1 0.547 0.553 13.90 14.04 3 e2 0.238 0.273 6.05 6.93 4, 5 n28 286 nd 7 7 7 ne 9 9 7 rev. 0 7/98 notes: 1. controlling dimension: inch . converted millimeter dimen- sions are not necessarily exact. 2. dimensions and tolerancing per ansi y14.5m-1982. 3. dimensions d1 and e1 do not include mold protrusions. al- lowable mold protrusion is 0.010 inch (0.25mm) per side. dimensions d1 and e1 include mold mismatch and are mea- sured at the extreme material condition at the body parting line. 4. to be measured at seating plane contact point. 5. centerline to be determined where center leads exit plastic body. 6. ?n? is the number of terminal positions. 7. nd denotes the number of leads on the two shorts sides of the package, one of which contains pin #1. ne denotes the num- ber of leads on the two long sides of the package. -c-

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